Latches / Flip-Flops

A flip-flop refers to an circuit that has two stable states and thereby is capable of serving as one bit of memory.

A flip-flop is usually controlled by one or two control signals and/or a gate or clock signal.



SR (Set-Reset) flip-flops

This is a fundamental latch. The stored bit is present on the output marked Q.

If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high even after S returns low; similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low even after R returns low.


T (Toggle) flip-flops

T is the toggle input and Q is the stored data output.

If the T input is high, the T flip-flop changes state ("toggles").
If the T input is low, the flip-flop holds the previous value.


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JK flip-flop

The JK flip-flop acts as a SR flip-flop (J=Set, K=Reset) by toogling the output when S = R = 1.

The combination J = 1, K = 0 is a command to set the flip-flop;
the combination J = 0, K = 1 is a command to reset the flip-flop
and the combination J = K = 1 is a command to toggle the flip-flop.

The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.
To synthesize a D flip-flop, simply set K equal to the complement of J.


D flip-flop

The Q output always takes on the state of the D input at the moment of a rising clock edge.

It is called D flip-flop because the output takes the value of the D (Data) input, and Delays it by one clock count.

The D flip-flop can be seen as a simple memory cell, zero-order hold, or delay line.


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Master-slave (pulse-triggered) D flip-flop

A master-slave D flip-flop is created by connecting two gated D latches in series, and inverting the enable input to one of them.
It is called master-slave because the second latch in the series only changes in response to a change in the first (master) latch.
The term pulse triggered means that data are entered on the rising edge of the clock pulse, but the output doesn't reflect the change until the falling edge of the clock pulse.